Assertion to calculate and verify time difference between 2 states

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Hi Ben,


property calc_rate (state_e sta, stb, int rate);
        realtime current_time;
        disable iff(a)
        ($changed(state) && state==sta, current_time = $realtime) |-> 
         first_match(##[1:$] state==stb) ##0 ($realtime - current_time) == rate;
endproperty: calc_rate

In the above property instead of keeping track of specific states, will the property work if we use $changed in the first_match of the consequent statement?