Assertion property in SystemVerilog

SystemVerilog
, ,
1

Hi, Can anyone help me understanding this property? It is for APB protocol.


property PSEL_ASSERT_SIGNAL_STABLE(PSEL);
  @(posedge PCLK)
  (!$stable(PSEL) && $onehot(PSEL)) |-> $stable(PSEL)[*1:$] ##1 $fell(PENABLE);
endproperty: PSEL_ASSERT_SIGNAL_STABLE

I understood the first condition before implication operator. It says PSEL will change its state and after changing its value only 1 bit of PSEL will become 1 and all others zero. At this time this condition will become true.
But facing difficulty in understanding part after |-> .
stable(PSEL)[*1:] mean that PSEL will be stable for at least 1 clock and
##1 $fell(PENABLE) mean that after 1 cycle delay PENABLE will become 0. But I am not able to make relation between |->, stable(PSEL)[*1:] and ##1 $fell(PENABLE).

Thank you In advance.

2

In reply to vickydhudashia:

There is a problem with the
(!$stable(PSEL) && $onehot(PSEL)) |-> stable(PSEL)[*1:] ##1 $fell(PENABLE);
because it will ALWAYS FAIL; You cannot have !$stable(PSEL) AND**$stable(PSEL)** in the SAME cycle!
The fix

property PSEL_ASSERT_SIGNAL_STABLE(PSEL);
@(posedge PCLK)
(!$stable(PSEL) && $onehot(PSEL)) |=> $stable(PSEL)[*1:$] ##1 $fell(PENABLE);
endproperty: PSEL_ASSERT_SIGNAL_STABLE

$stable(PSEL)[*1:$] ##1 $fell(PENABLE);
// is equivalent to:
$stable(PSEL)[*1] ##1 $fell(PENABLE) or
$stable(PSEL)[*2] ##1 $fell(PENABLE) or
...
$stable(PSEL)[*n] ##1 $fell(PENABLE); // when "n" is infinity
// This sequence will succeed only when at some cycle 
// $stable(PSEL)==1 AND at the next cycle $fell(PENABLE)==1

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Thank you ben for your response.
I was studying APB3 protocol Verification from verification academy. Here is the link.

Just attaching link to this conversation so anyone in future can refer to this question.

https://verificationacademy.com/cookbook/coverage/apb3_protocol_monitor


// FROM PSEL being active, then signal must be stable until end of cycle
property PSEL_ASSERT_SIGNAL_STABLE(signal);
  @(posedge PCLK)
  (!$stable(PSEL) && $onehot(PSEL)) |-> $stable(signal)[*1:$] ##1 $fell(PENABLE);
endproperty: PSEL_ASSERT_SIGNAL_STABLE
 
PSEL_STABLE: assert property(PSEL_ASSERT_SIGNAL_STABLE(PSEL));
4

In reply to vickydhudashia:
Well, as humans, we make mistakes.
Assertions, particularly if complex, should be tested, I have in my SVA 4th Edition book, a chapter about verifying assertions. Below is an example in verifying this particular assertions using my guidelines:


import uvm_pkg::*; `include "uvm_macros.svh" 
module stb; 
	bit pclk, enb;  
	bit[3:0] psel;
	default clocking @(posedge pclk); endclocking
	initial forever #10 pclk=!pclk;   
	
	property PSEL_ASSERT_SIGNAL_STABLE(psel);
     @(posedge pclk)
      (!$stable(psel) && $onehot(psel)) |-> $stable(psel)[*1:$] ##1 $fell(enb);
    endproperty: PSEL_ASSERT_SIGNAL_STABLE
    apsel_ASSERT_SIGNAL_STABLE:  assert property(PSEL_ASSERT_SIGNAL_STABLE(psel));  
    
    property PSEL_ASSERT_SIGNAL_STABLE2(psel);
     @(posedge pclk)
      (!$stable(psel) && $onehot(psel)) |=> $stable(psel)[*1:$] ##1 $fell(enb);
    endproperty: PSEL_ASSERT_SIGNAL_STABLE2
    apsel_ASSERT_SIGNAL_STABLE2:  assert property(PSEL_ASSERT_SIGNAL_STABLE2(psel));  
 initial begin 
     repeat(200) begin 
       @(posedge pclk);   
       if (!randomize(psel, enb)  with 
           { psel dist {4'b1000:=1, 4'b0001:=3};
             enb dist {1'b1:=1, 1'b0:=7};
           }) `uvm_error("MYERR", "This is a randomize error")
       end 
       $finish; 
    end 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115