Assertion property in SystemVerilog

SystemVerilog
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2

In reply to vickydhudashia:

There is a problem with the
(!$stable(PSEL) && $onehot(PSEL)) |-> stable(PSEL)[*1:] ##1 $fell(PENABLE);
because it will ALWAYS FAIL; You cannot have !$stable(PSEL) AND**$stable(PSEL)** in the SAME cycle!
The fix

property PSEL_ASSERT_SIGNAL_STABLE(PSEL);
@(posedge PCLK)
(!$stable(PSEL) && $onehot(PSEL)) |=> $stable(PSEL)[*1:$] ##1 $fell(PENABLE);
endproperty: PSEL_ASSERT_SIGNAL_STABLE

$stable(PSEL)[*1:$] ##1 $fell(PENABLE);
// is equivalent to:
$stable(PSEL)[*1] ##1 $fell(PENABLE) or
$stable(PSEL)[*2] ##1 $fell(PENABLE) or
...
$stable(PSEL)[*n] ##1 $fell(PENABLE); // when "n" is infinity
// This sequence will succeed only when at some cycle 
// $stable(PSEL)==1 AND at the next cycle $fell(PENABLE)==1

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
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