Assertion property in SystemVerilog

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Thank you ben for your response.
I was studying APB3 protocol Verification from verification academy. Here is the link.

Just attaching link to this conversation so anyone in future can refer to this question.

https://verificationacademy.com/cookbook/coverage/apb3_protocol_monitor


// FROM PSEL being active, then signal must be stable until end of cycle
property PSEL_ASSERT_SIGNAL_STABLE(signal);
  @(posedge PCLK)
  (!$stable(PSEL) && $onehot(PSEL)) |-> $stable(signal)[*1:$] ##1 $fell(PENABLE);
endproperty: PSEL_ASSERT_SIGNAL_STABLE
 
PSEL_STABLE: assert property(PSEL_ASSERT_SIGNAL_STABLE(PSEL));