In reply to ben@SystemVerilog.us:
A much much easier solution for the detection of a sync pattern in a stream:
bit[15:0] sync=16'b1101110100001101, log;
always_ff @(posedge clk or negedge rst_n) begin
if(!rst_n) log=0;
else log<= {a, log[14:0]};
a_sync: assert(log[15:8]==sync[15:8] && log[7:4]!=1101 && log[3:0] == sync[3:0])
detected = 1; else detected=0;
end
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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