In reply to Jeff_Li_90:
- Looking for a sync pattern of 16 bits
a a !a a; a a !a a; not(a a !a a); a a !a a; - If you have a good first 4 bits, you want to exclude the other attempts
- My untested approach is to use a lock to start.
This should resolve your 1101101 - The unlock resets if it fails to find a match.
TWO SOLUTIONS: COMPLEX ONE HERE, SIMPLER ONE IN THE REPLY
// NEEDS TESTING BADLY. WAY TOO COMPLEX OF AN APPROACH
bit clk, a, b, c, rst_n, lock, detected;
function void set_lock(bit q);
if(q) lock <=1'b1;
else lock <= 1'b0;
endfunction
sequence seq1101_to_det; @(posedge clk) a ##1 a ##1 !a ##1 a; endsequence
// 16 bits sequence a a !a a; a a !a a; not(a a !a a); a a !a a;
// put a lock 12 bits <--------------------------------->
ap_detected: assert property(
@(posedge clk) disable iff(rst_n==0)
lock==0 ##4 (seq1101_to_det.triggered, set_lock(1)) ##4
( (seq1101_to_det.triggered ##4
!seq1101_to_det.triggered ##4
(seq1101_to_det.triggered, set_lock(0)))) //intersect 1[*12])
|=> detected) else set_lock(0);
ap_no_sync_TF: assert property( // pattern no pattern
@(posedge clk) disable iff(rst_n==0)
lock==0 ##4 seq1101_to_det.triggered ##4
(!seq1101_to_det.triggered, set_lock(0)));
ap_no_sync_TTT: assert property( // 3 sequences od same pattern
@(posedge clk) disable iff(rst_n==0)
lock==0 ##4 seq1101_to_det.triggered ##4
seq1101_to_det.triggered ##4
(seq1101_to_det.triggered, set_lock(0)));
ap_no_sync_TTTT: assert property( // 4 sequences od same pattern
@(posedge clk) disable iff(rst_n==0)
lock==0 ##4 seq1101_to_det.triggered ##4
seq1101_to_det.triggered ##4
seq1101_to_det.triggered ##4
(seq1101_to_det.triggered, set_lock(0)));
After some more thoughts, there is no need for that “lock” concept.
At every clocking event there is a need to look for async pattern.
Let me if this works out.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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