Assertion for counting clock cycles during reset pulse

SystemVerilog
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4

In reply to spoiled rabbit:
Apologies for my mistake; it always helps to test the code :)
The concept is correct. Below is code that works OK.
Instead of detecting a $fell that relies on the clock, I used
always @(negedge reset) begin : b0


/* https://verificationacademy.com/forums/systemverilog/assertion-counting-clock-cycles-during-reset-pulse */ 
module top;  
    bit clk, reset;
    let period=10ns; 
    event eclk, eanalog; 
    initial forever #5 clk=!clk;  

  
  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
      #0  reset = 1;
      #100 reset = 0;
           force clk = 0;
      #500 release clk;
      #0 reset = 1;
      #100 $finish;
  end
 
    always @(negedge reset)  begin : b0
      bit got_2clk, done; 
      // if($fell(reset, @(posedge clk)))
       begin  : fall_reset
        fork
          begin : one 
            repeat(2) @(posedge clk); 
            got_2clk=1'b1; 
            done=1'b1; 
            -> eclk; 
          end  : one 
 
          begin : two 
            #(period*2 +1); 
            done=1'b1; 
            ->eanalog;
          end : two
        join_none
        wait(done);
        a_2clk: assert(got_2clk); // 2clk is active
        got_2clk=1'b0; 
        done=1'b0; 
      end : fall_reset        
    end  : b0
 
 endmodule

Sim result

ASSERT: Error: ASRT_0301 testbench.sv(40): Immediate assert condition “a_2clk” FAILED at time: 121ns, scope: top

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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