Assertion for counting clock cycles during reset pulse

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for your reply.
I played around with your implementation but if I made no mistake, then it can’t catch that scenario when the reset gates the clk immediately: https://www.edaplayground.com/x/859J (I hope EDA Playground links are allowed)

This solution is dependent on the clk so it is supposed to ‘check itself’ somehow - that’s why I thought that it can’t be solved without an auxiliary clk.