Assertion for counting clock cycles during reset pulse

SystemVerilog
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2

In reply to spoiled rabbit:
// Comment on your solution


// Add the fast clk 
// You can add an test 
let n=20;  // Am guessing at the 20, need to specify
property count_cycles;
    int cnt;
    @(posedge fastclk) ($fell(reset), cnt = 0 )|=> 
        first_match( (CLK_PULSE, ++cnt) [*0:$] 
                      ##1 (reset, $display("cnt:%d", cnt))) 
                     ##0 cnt >= n;
  endproperty

Can this be solved without using an auxiliary faster clock?

Yes, by using fork-joine_none. Basically, you fire 2 tasks: a 2-clock task and a timeout task. If timeout, then failure. See my paper Understanding the SVA Engine, link below. Note that an assertion can be expressed in many forms; SVA is one way.


module top;  
    bit clk, reset;
    let period=10ns; 
    initial forever #5 clk=!clk;  
    // <<<<<<<<<<<<<SEE my response for the correction >>>             
    always @(posedge clk)  begin : b0  // SEE BELOW, THIS IS IN ERROR 
    // Should be 
    //  always @(negedge reset)  begin : b0
      bit got_2clk, done; 
      if($fell(reset, @(posedge clk))) // IN ERROR, comment this out 
       begin  : fall_reset
        fork
          begin : one 
            repeat(2) @(posedge clk); 
            got_2clk=1'b1; 
            done=1'b1; 
          end  : one 

          begin : two 
            #(period*2 +1); 
            done=1'b1; 
          end : two
        join_none
        wait(done);
        a_2clk: assert(got_2clk); // 2clk is active
        got_2clk=1'b0; 
        done=1'b0; 
      end : fall_reset        
    end  : b0

    initial begin 
       #100; 
       $finish;
    end 
 endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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