Assertion :- check the signal is asserted whenever count value exceed to 64

SystemVerilog
,
12

In reply to rkg_:
You can use the generatestatement as shown below;


module top;
    bit i_ref_clk, refclk_en_fll_sync, refclk_output;
    bit[3:0] i_refclk_div; 
// -------------------------------------------------------------------------------
    generate for (genvar i=0; i<=3; i++)
        begin 
            p_ref_clk: assert property(@(posedge i_ref_clk) 
               ( $rose(refclk_en_fll_sync) &&  i_refclk_div == i+1 ) -> 
                                   refclk_output==!$past(refclk_output, 2**i));
        end
    endgenerate
// ---------------------------------------------------------------------------------
   p_ref_clk2: assert property(@(posedge i_ref_clk) 
     ( $rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0001 ) -> 
                                   refclk_output==!$past(refclk_output));
 
   ap_ref_clk4: assert property(@(posedge i_ref_clk) 
     ($rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0010) |-> 
                                   refclk_output==!$past(refclk_output,2));
 
   ap_ref_clk8: assert property(@(posedge i_ref_clk) 
     ($rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0011) |-> 
                                   refclk_output==!$past(refclk_output,4));

   ap_ref_clk16: assert property(@(posedge i_ref_clk)
      ($rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0100) |-> 
                                   refclk_output==!$past(refclk_output,8));

endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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