Assertion :- check the signal is asserted whenever count value exceed to 64

SystemVerilog
,
11

In reply to ben@SystemVerilog.us:

Hi Ben,

I have clock divider in my design and i want to verify the functionality through the assertion.

→ ref_clk is put to divider and refclk_output is output and based on refclk_div it will divide the ref_clk frequency.

ap_ref_clk2: assert property(@(posedge i_ref_clk) ( $rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0001 ) -> refclk_output==!$past(refclk_output));


ap_ref_clk4: assert property(@(posedge i_ref_clk) ($rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0010) |-> 
                          refclk_output==!$past(refclk_output,2));



ap_ref_clk8: assert property(@(posedge i_ref_clk) ($rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0011) |-> 
                          refclk_output==!$past(refclk_output,4));


ap_ref_clk16: assert property(@(posedge i_ref_clk) ($rose(refclk_en_fll_sync) &&  i_refclk_div == 4'b0100) |-> 
                          refclk_output==!$past(refclk_output,8));[/systemverilog



Is their any better approch to write the assertion for different value of refclk_div (supported till divide by 32768 i.e. refclk_div == 4'b1111 )