Advise for Case Statement

SystemVerilog
, , ,
1

Hi
I am looking for a way to write the following case statement below.
aaa is 32-bit and presumably one-shot but has a default all zeros
unique statement should report warning if any 2-bits are high at the same time.
The code below doesn’t give me the result I need.

always @ (*)
    unique case (1'b1) inside
      aaa[14:30]: begin 
	CMP1A = some value;
	CMP1B = some value;
      end
      aaa[5:6],aaa[9]: begin 
	CMP1A = some value;
	CMP1B = some value;
      end
      aaa[3]: begin 
	CMP1A = some value;
	CMP1B = some value;
      end
      aaa[4],aaa[8]: begin 
	CMP1A = some value;
	CMP1B = some value;
      end
      default: begin
	CMP1A = some value;
	CMP1B = some value;
      end
   endcase

Your assistance is much appreciated.

2

In reply to sonofthesand:

You cannot use unique case here unless are willing to make a seperate case item for each bit. Also, aaa[5:6] needs to be broken out as aaa[5],aaa[6].

If you want to know when more than 1 bit of aaa is set, use an assertion.

always_comb begin
    assert final ($onehot0(aaa));
    case (1'b1)
3

In reply to dave_59:

In reply to sonofthesand:
You cannot use unique case here unless are willing to make a seperate case item for each bit. Also, aaa[5:6] needs to be broken out as aaa[5],aaa[6].
If you want to know when more than 1 bit of aaa is set, use an assertion.

always_comb begin
assert final ($onehot0(aaa));
case (1'b1)

Thank you for your suggestion.
I have also come to realise that unique doesn’t work even if I were to separate the bits in a case item like below which makes this feature limited.

always_comb begin
unique case (1’b1) inside
aaa[5],aaa[6]: begin
CMP1A = some value;
CMP1B = some value;
end

4

In reply to sonofthesand:

If you want use unique case, you would have to write it as

always_comb begin
unique case (1'b1)
aaa[5]: begin
CMP1A = some value;
CMP1B = some value;
end
aaa[6]: begin
CMP1A = some value;
CMP1B = some value;
end
5

In reply to dave_59:

In reply to sonofthesand:
If you want use unique case, you would have to write it as

always_comb begin
unique case (1'b1)
aaa[5]: begin
CMP1A = some value;
CMP1B = some value;
end
aaa[6]: begin
CMP1A = some value;
CMP1B = some value;
end

Got it. Thank you for your help!