Advise for Case Statement

SystemVerilog
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4

In reply to sonofthesand:

If you want use unique case, you would have to write it as

always_comb begin
unique case (1'b1)
aaa[5]: begin
CMP1A = some value;
CMP1B = some value;
end
aaa[6]: begin
CMP1A = some value;
CMP1B = some value;
end