Advise for Case Statement

SystemVerilog
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2

In reply to sonofthesand:

You cannot use unique case here unless are willing to make a seperate case item for each bit. Also, aaa[5:6] needs to be broken out as aaa[5],aaa[6].

If you want to know when more than 1 bit of aaa is set, use an assertion.

always_comb begin
    assert final ($onehot0(aaa));
    case (1'b1)