A problem when using $past() for systemverilog assertion

SystemVerilog
, , ,
6

In reply to ben@SystemVerilog.us:

Hi, Ben,

Thanks so much for your detailed information.

Last quick question : After we used @(posedge clk) as clock even for an assertion as following, the value inside the expression will still be sampled value just before the posedge clock, is that right ?

a_inside255 : assert property (@(posedge clk) a >= 0 && a < 255);

The “a” is always refer to the value before the posedge clk, is that right ? Namely, sampled value in Preponed Region ?

Thanks,

WangYang