A problem when using $past() for systemverilog assertion

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Hi, Ben,

Thanks again for your great information.

I still have question on @(SAMPCNT). I didn’t get your point there. In Verilog LRM, @(SAMPCNT) will be explained by “any value changed”, so why I can’t use this expression here to indicate whenever the SAMPCNT changed, is there any side-effect ?

Since I am new to SVA, so thanks for your patience :-)

WangYang