In reply to ben@SystemVerilog.us:
$rose(gnt) |-> s_req.triggered;
For the triggered solution to work, use this sequence declaration
sequence s_req;
@(posedge clk). // updated.
first_match($rose(req) ##[1:$] gnt; // ##1 1'b1); // endpoint 1 cycle after gnt
endsequence
// the endpoint of the sequence must end when
// the $rose(gnt) occurs
// Note: This solution has many threads for each successful attempt
Read my paper Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2