A grant must at some time have been preceded by a request

SystemVerilog
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7

In reply to DVtrojan:

  • rose(req) ##[1:] 1’b1; // after the 1st req you get an endpoint at every cycle thereafter, till infinity.
  • The 1st attempt with the rose gnt would be OK. However,
  • $rose(gnt) |-> s_req.triggered;
    with any 2nd, 3rd, …nth grant the assertion would would be immediately passed.
    This is because the sequence (rose(req) ##[1:] 1’b1) is causing and endpoint at every cycle after the 1st rose of req