In reply to jianfeng.he:
Please use code tags making your code easier to read. I have added them for you.
This has to do with namespaces, which there are several in SystemVerilog, and the way packages are defined.
The names of modules and interfaces exist in a global definitions name space. You can always reference a module or interface name before it has been defined. Note that an instance name (or hierarchical reference is not the same as the definition name
Classes are user defined types which can be declared in a number of local namespaces. Packages are defined in such a way that you can only reference local names declared inside the same package, or imported from another package that has already been defined.
See section 3.13 Name spaces and 26.3 i]Referencing data in packages[/i] in the IEEE 1800-2017 SystemVerilog LRM for more details.