Why can an interface be recognized in a package, but a class cannot

SystemVerilog
,
1

Hi:
Can someone help explain why an interface can be recognized in a package, but a class cannot?

Example Code here which gives an error about the AA, but base_intf works OK

class AA;
endclass

interface base_intf();
  logic [3:0] in;
endinterface

package bfm_base_pkg；
//   typedef virtual base_intf vbif;
  typedef class AA;

  class base;
    protected virtual base_intf vif;
    AA classA;
  endclass
endpackage

Error-[SV-UFCD] Undefined forward class declaration
testbench.sv, 14
bfm_base_pkg, “AA”
The forward typedef of the class does not have a definition in the same
scope.
Please provide a definition to the forward class declaration.

2

In reply to jianfeng.he:

SystemVerilog supports separate compilation using compiled units.
compilation unit: A collection of one or more SystemVerilog source files compiled together.
The following items are visible in all compilation units: modules, primitives, programs, interfaces, and packages.

Try to add class AA declaration inside package. And use: import pkgBla::* in bfm_base_pkg

3

In reply to jianfeng.he:

Please use code tags making your code easier to read. I have added them for you.

This has to do with namespaces, which there are several in SystemVerilog, and the way packages are defined.

The names of modules and interfaces exist in a global definitions name space. You can always reference a module or interface name before it has been defined. Note that an instance name (or hierarchical reference is not the same as the definition name

Classes are user defined types which can be declared in a number of local namespaces. Packages are defined in such a way that you can only reference local names declared inside the same package, or imported from another package that has already been defined.

See section 3.13 Name spaces and 26.3 i]Referencing data in packages[/i] in the IEEE 1800-2017 SystemVerilog LRM for more details.