Variable clock generation in verilog using task

I have used following code to generate clock (whichever value i pass through task it will create that frequency), but the code only works if i use CLKSEL_global = clksel_local (line no. 23)(i.e. blocking assignment) but that creates delta delay.

 `timescale 1ns/1ps
module new(CLK,CLK_OUT);
input CLK;
output CLK_OUT;
 
and(CLK_OUT,1,CLK);
 
 
endmodule



`timescale 1ns/1ps
module tb();
real CLKSEL_global;
reg clk;
reg CLK7;
wire clk_out;
 
new dut(clk,clk_out);
 
task task_CLOCK;
 
input real clksel_local;
begin
CLKSEL_global = clksel_local;
 
end
endtask
 
initial begin
 CLK7 = 0;
 forever begin
  #(500.0/CLKSEL_global) CLK7 = 1;
  #(500.0/CLKSEL_global) CLK7 = 0;
 end
end
 
always @(CLK7) begin
   clk = CLK7;
 end
 
 initial begin
task_CLOCK(340.0);
  end
  
 initial begin
 #100 $finish ;
 end
 endmodule

How do i generate variable clock without introducing delta delay ?? or is their other way than using a task

Thank you in advance