[SystemVerilog] Bit/Logic datatype for edge detector

SystemVerilog
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1

Hi everyone,

Recently I faced an issue with edge detector using bit/logic type in SystemVerilog. It seems that the behavior is incorrect. I had to change the variables type back to old Verilog wire/reg to make it works.

Could anyone please help me to explain why do we have this type issue?

EDA Playground Link: Bit/Logic issue for edge detector - EDA Playground

Thank you,
-An

2

In reply to AnPham:

I’m assuming you mean you are seeing functional differences between these two declarations:

bit detect = dd & !d; // issue
wire detect = dd & !d; // ok

This is because the first is a variable declaration with an initialization that executes before time 0. The second is a net declaration with a continuous assignment.

If you want the same behavior, you need to write the variable declaration and continuous assignment separately.

bit detect;
assign detect = dd & !d;
3

In reply to dave_59:

That is subtle. SV, the glorious Franken-language.

4

In reply to warnerrs:

BTW, this behavior is from Verilog-2001. You can replace
bit with
reg in the original code.

5

In reply to dave_59:

I got it. It works now. Thank you Dave.
-An