[SystemVerilog] Bit/Logic datatype for edge detector

In reply to AnPham:

I’m assuming you mean you are seeing functional differences between these two declarations:

bit detect = dd & !d; // issue
wire detect = dd & !d; // ok

This is because the first is a variable declaration with an initialization that executes before time 0. The second is a net declaration with a continuous assignment.

If you want the same behavior, you need to write the variable declaration and continuous assignment separately.

bit detect;
assign detect = dd & !d;