[SystemVerilog] aliases for tasks/functions

SystemVerilog
1

Hi All,

In SystemVerilog, is it possible to use aliases for tasks/functions?

Let’s say I have a task named t1 anybody a function named f1 .

Is there a way (besides copy/paste) to define the same tasks/functions with another name?

Reason? Depending on the code context, people sometimes call to the same things with different names…

Thank you!

2

In reply to dmitryl:

You can always create a wrapper.

function int f1(bit arg1);
 ...
 return expression;
endfunction

function int f2(bit arg1);
  return f1(arg1);
endfunction
3

In reply to dave_59:

Is there a way to define an alias for a module instance? thank you

4

In reply to dmitryl:

Create a wrapper.

The only two true alias mechanisms in SystemVerilog. the alias construct for renaming wires, and the let construct for general expressions.

5

In reply to dave_59:

could you please let me know an useful example for a let construct?

why was it introduced into the language? what problem does it come to solve?

6

In reply to dmitryl:

The let construct was introduced by the committee working on assertions. They wanted functions that had arguments that did not necessarily have a data type, like passing
@(posedge clk), not just clk. They wanted other features that essentially made the construct expand like a text macro. But the problem with a text macro is that it has global compilation unit scope, and if you redefine a macros, it replaces the old definition. A function, on the other hand, has a local scope.

So they came up with the let construct to more formally represent a symbol for an arbitrary expression.