Sequence in Sensitivity List

Question

Hi ,

Consider the following code ::

  sequence  sr1;
    @( posedge clk ) req ##2 gnt ;
  endsequence
 
  always @( sr1 )   //  Doubt  regarding  the  triggering 
    $display(" TIME : %3t  Sequence  sr1  completes " , $time)

According to SV Region always procedural block executes in Active region

Since sequence expression is evaluated in Observed region ( using values sampled in preponed region ) , can I state the following ::

(a)If Sequence ' sr1 ' completes , internally the event control ' sr1 ' gets triggered in Observed region , which causes @( sr1 ) to unblock in Active region .

(b) This is an example of re-entry from Observed region to Active region in SV Region.

Answer 1

dave_59

Forum Moderator

10660 posts

January 05, 2023 at 6:52 pm

In reply to Have_A_Doubt:

Correct. You cannot change the region a procedural block executes in once started.

— Dave Rich, Verification Architect, Siemens EDA

Answer 2

Solution

ben@SystemVerilog.us

Full Access

2600 posts

January 05, 2023 at 7:10 pm

In reply to Have_A_Doubt:

I would say YES to both.
From 1800'2017:4.5 SystemVerilog simulation

execute_time_slot {
  execute_region (Preponed);
    execute_region (Pre-Active); 
      while (any region in [Active ... Pre-Postponed] is nonempty) {
          while (any region in [Active ... Post-Observed] is nonempty) {
             execute_region (Active);
             R = first nonempty region in [Active ... Post-Observed];
             if (R is nonempty)
                move events in R to the Active region; // **1**
          }
          while (any region in [Reactive ... Post-Re-NBA] is nonempty) {
            execute_region (Reactive);
            R = first nonempty region in [Reactive ... Post-Re-NBA];
            if (R is nonempty)
                move events in R to the Reactive region;
          }
          if (all regions in [Active ... Post-Re-NBA] are empty)
             execute_region (Pre-Postponed);
       }
       execute_region (Postponed);
}

With your code:

sequence  sr1;
    @( posedge clk ) req ##2 gnt ;
  endsequence
 
  always @( sr1 )   //  Doubt  regarding  the  triggering 
    $display(" TIME : %3t  Sequence  sr1  completes " , $time)

The @(posedge clk) start the time step. Within that time step you have all these regions.
In the Observed region sr1 is evaluated to be a match or no-match.
The algortithm says:
R = first nonempty region in [Active ... Post-Observed];
if (R is nonempty)
move events in R to the Active region; // **1**
In that Active region, in the loop-back, the event @(sr1) is true and the always @( sr1 ) is executed.
That's how I see it.
Ben Cohen
http://www.systemverilog.us/
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
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https://verificationacademy.com/verification-horizons/july-2022-volume-18-issue-2/reflections-on-users-experiences-with-sva-part-2
Understanding and Using Immediate Assertions
https://verificationacademy.com/verification-horizons/december-2022-volume-18-issue-3/understanding-and-using-immediate-assertions
SUPPORT LOGIC AND THE ALWAYS PROPERTY
http://systemverilog.us/vf/support_logic_always.pdf
SVA Alternative for Complex Assertions
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SVA in a UVM Class-based Environment
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SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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Answer 3

Have_A_Doubt

Forum Access

173 posts

January 05, 2023 at 9:57 pm

Thank you Dave and Ben .

Unfortunately can't mark both as Solution :(

Answer 4

hisingh

Full Access

139 posts

January 08, 2023 at 12:30 pm

In reply to ben@SystemVerilog.us:

Ben ,

Typically we require assert / cover property for a property / sequence to run ( Similar to a module instance required for the logic within it to work )

How is it that the sequence is running without writing it as ::

 assert  property ( sr1 ) ;  
   [ OR ]  
 cover  property ( sr1 ) ;

Is this a feature of a SVA sequence that isn't there for SVA property ?

Answer 5

ben@SystemVerilog.us

Full Access

2600 posts

January 08, 2023 at 2:28 pm

In reply to hisingh:

But there is an implicit run when the sequence is used, like your:
always @( sr1 )

Answer 6

hisingh

Full Access

139 posts

January 09, 2023 at 12:43 am

In reply to ben@SystemVerilog.us:

Oh I see . I believed that only assert / cover property would cause sequence to run .

What decides the no. of time a sequence executed via event control ?
Will it depend on the no. of time the blocking event @( sequence_name ) occurs ? OR
Will it execute till end of simulation irrespective of the no. of times the blocking event is present

  sequence  sr1 ;
    @( posedge clk1 ) req1 ##2 gnt1 ;
  endsequence
 
  sequence  sr2 ;
    @( posedge clk2 ) req2 ##2 gnt2 ;
  endsequence
 
    initial  begin
      @( sr1 ) ;  //  Blocking  event  present  only  once 
      $display(" Sequence sr1  within  initial completes ");
    end
 
    initial  begin
      #10 ;
      @( sr2 ) ;
      $display(" Sequence sr2  within  initial  completes ");
      #10 ;
      @( sr2 ) ;
      $display(" Sequence sr2  within  initial  completes again");
    end

For the 1st initial block does the sequence sr1 execute only once at time 0 when it's blocked at @( sr1 ) ?
OR will sequence sr1 continue execution till simulation end ? Even after time 0 when there is no event waiting for it ?

Similarly for the 2nd initial block will the sequence sr2 execute only twice ( since @( sr2 ) occurs twice ) ?

Whereas if I were to write ::

   assert  property ( sr1 );  // Could  also  be  cover  property ( sr1 ); 
 
   assert  property ( sr2 );  // could  also  be  cover  property ( sr2 ); 
 
   always @( sr1 )  $display(" Sequence sr1  within  always completes ");
 
   always @( sr2 )  $display(" Sequence sr2  within  always completes ");

I know the sequences sr1 and sr2 would execute on each posedge of clk1 and clk2 respectively till end of simulation

Answer 7

ben@SystemVerilog.us

Full Access

2600 posts

January 09, 2023 at 8:44 am

In reply to hisingh:
The sequence has to be checked as it cannot know for a more complex sequence when the match might occur. However, some optimization can be done if the compiler knows that it is used only once in time, e.g., in an initial block without a loop. The compiler could then make it so that the sequence runs only until used.
On the other hand, this situation is rare, and it may not pay to implement such optimization in particular if it must determine any cross-module reference from other modules related to the sequence (i.e., most likely it is not done, and the sequence keeps running).

Answer 8

hisingh

Full Access

139 posts

January 09, 2023 at 9:05 am

In reply to ben@SystemVerilog.us:

Thanks Ben .

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