The question about truncation with 32 bits and 8 bits in systemverilog

here is some code I wrote for a simple case.

typedef byte unsigned uint8;
typedef int  unsigned uint32;
uint8  mem_data[];
uint32 my_data[];
my_data = new[1024];
mem_data = new[4096];
for(int i = 0; i < 1024; i++) begin
    my_data[i] = 'h12345678;
end
for (int idx = 0; idx < 1024*4; idx+=4) begin
    mem_data[idx]   = my_data[idx/4][7:0];
    mem_data[idx+1] = my_data[idx/4][15:8];
    mem_data[idx+2] = my_data[idx/4][23:16];
    mem_data[idx+3] = my_data[idx/4][31:24];
end

and I tried to run this case and the mem_data is empty. I am not sure how to fix it. Please kindly give me a help. Thank you

In reply to zz8318:

You need to specify the size of your dynamic arrays with the ‘new’ constructor.

In reply to sbellock:

Actually I have this code (sorry to forget paste that line in my original post)

In reply to zz8318:

With that change it works fine for me on Questa. mem_data is fully populated.

In reply to zz8318:

I have another question here.

Is there any big difference between these two types shown below ?

int unsigned and logic[31:0]

byte unsigned and logic[7:0]

In reply to sbellock:
And you can do this without for loops by using the streaming operator

module top;
  typedef byte unsigned uint8;
  typedef int  unsigned uint32;
  uint8  mem_data[];
  uint32 my_data[];
  initial begin
     my_data = new[16];
     my_data = '{default:'h12345678};
     mem_data = {<<uint32{ {<<uint8{my_data}} }};
     $displayh("%p",mem_data);
end
endmodule

Also, it helps to show a complete example that one can cut & paste to run, like I just did.

In reply to zz8318:

In reply to zz8318:
I have another question here.
Is there any big difference between these two types shown below ?
int unsigned and logic[31:0]
byte unsigned and logic[7:0]

There is no difference within the SystemVerilog language. There is a slight difference when using the DPI. The int and byte types are C compatible and arguments can be directly accessed from the C side. Packed arrays use bit access methods.
–UPDATE–

Just noticed you used logic, not bit. My answer applies to 2-state bit.

In reply to dave_59:

It works when I tried your suggestion. Thanks you