The question about truncation with 32 bits and 8 bits in systemverilog

SystemVerilog
6

In reply to sbellock:
And you can do this without for loops by using the streaming operator

module top;
  typedef byte unsigned uint8;
  typedef int  unsigned uint32;
  uint8  mem_data[];
  uint32 my_data[];
  initial begin
     my_data = new[16];
     my_data = '{default:'h12345678};
     mem_data = {<<uint32{ {<<uint8{my_data}} }};
     $displayh("%p",mem_data);
end
endmodule

Also, it helps to show a complete example that one can cut & paste to run, like I just did.