The question about truncation with 32 bits and 8 bits in systemverilog

SystemVerilog
7

In reply to zz8318:

In reply to zz8318:
I have another question here.
Is there any big difference between these two types shown below ?
int unsigned and logic[31:0]
byte unsigned and logic[7:0]

There is no difference within the SystemVerilog language. There is a slight difference when using the DPI. The int and byte types are C compatible and arguments can be directly accessed from the C side. Packed arrays use bit access methods.
–UPDATE–

Just noticed you used logic, not bit. My answer applies to 2-state bit.