I have an RTL design(suppose it’s name is dut.v) which is writen in verilog, and a testbench(suppose it’s name is tb.sv) which is writen in systemverilog. When I simulate my RTL using vcs, I add “-sverilog” option to support systemverilog. But I find a problem: vcs will compile both dut.v and tb.sv as systemverilog. This is not what I wanted.
I hope vcs compiling dut.v as verilog, and compiling tb.sv as systemverilog. How can I achieve my goal ? Is there any options to tell vcs “just compile files as their file extensions”? i.e. compile *.v file as verilog, and compile *.sv as systemverilog. I know irun(cadence EDA tool) can do this. But I don’t know how to tell vcs do this. If I remove “-sverilog” option, it will compile all files as verilog and will report compile error when compile tb.sv.
Then I will explain why I want vcs to compile dut.v as verilog.
If there are below lines of code in dut.v:
reg aa;
assign aa = sel ? bb : cc;
Actually these code is not correct, below aa should be decleared as wire, but not reg. But, if this file is compiled as systemverilog, it will not report error. This is not what I wanted.
(I wonder if these code can be synthesised correctly and will not report error?)
You need to contact Synopsys about their tool support.
Modelsim/Questa, like most other tools will recognize files with *.sv extension as SystemVerilog and you can use -sv to treat all files as SystemVerilog. The code you show is legal for SystemVerilog, but was not legal in Verilog. Most synthesis tools support this syntax for SystemVerilog as you are allowed to have a single continuous assignment to a variable.
In either verilog/SV your code should be reported as a error.(Not sure whether there are exceptions to this statement)
Use compile directives to force the tool to use verilog keywords in a file.
Thank you very much, Dave!
Another question: you said that this syntax is supported by most synthesis tools, is there any IEEE standard about “Systemverilog synthesis syntax”? I have searched for a long time, but didn’t find this kind of standard document.
No, you are not right.
If you compile this code as verilog, all tools(I only tried VCS and iRUN, but I think other tools will report same result)will report error. If you compile this code as systemverilog(vcs -sverilog, irun -sv), both tools will pass and not report error.
You can try it.
monkeyking, Verilog IEEE 1364.1-2002 attempted to define a synthesis standard, but it was kind of pointless. None of the major synthesis vendors agreed to support it, and there is widespread differences in HDL synthesis support. You need to check with your synthesis vendor for what they support.
I’ve tried with +systemverilogext+.sv +verilog2001ext+.v, the result is very curious!
VCS does not report error when compile prevoius code, it seems that my code is compiled as SystemVerilog, right? But, if I add “logic” data type into my file – dut.v, then VCS will report error, it said that “logic” is unknown!
I’m confused! Whatever does VCS compile my design as when added “+systemverilogext+.sv +verilog2001ext+.v” ? If it compile dut.v as verilog, it will report error for prevoius code(assign value to a reg); but it does’t report error; If it compile dut.v as Systemverilog, why it does not recognize “logic”?