In reply to digeshpatel:
I’ve tried with +systemverilogext+.sv +verilog2001ext+.v, the result is very curious!
VCS does not report error when compile prevoius code, it seems that my code is compiled as SystemVerilog, right? But, if I add “logic” data type into my file – dut.v, then VCS will report error, it said that “logic” is unknown!
I’m confused! Whatever does VCS compile my design as when added “+systemverilogext+.sv +verilog2001ext+.v” ? If it compile dut.v as verilog, it will report error for prevoius code(assign value to a reg); but it does’t report error; If it compile dut.v as Systemverilog, why it does not recognize “logic”?
Can somebody help me?
Thanks very much!