Problem while using `ifdef..`elsif..`else

SystemVerilog
,
1

How to implement OR operation using defines?

for example,(snippet)
→ define DEF_1 define DEF_2
/////////////////////////////////
ifdef DEF_1 ifdef DEF_2

//Block of code that needs to be executed

endif endif

in the above case it behaves like an AND operation.i.e,if both DEF_1 and DEF_2 are defined then only the block will get executed.But I want to implement OR operation which means if either DEF_1 or DEF_2 are defined,then only the block should get executed.How can I do that?

Thanks
SATYA

2

In reply to SATYA369:

`ifdef DEF_1
  `define DEF_1OR2
`elsif DEF_2
  `define DEF_1OR2
`endif

`ifdef DEF_1OR2
//Block of code that needs to be executed
`endif
3

In reply to dave_59:

Thanks dave

Regards
SATYA