Parameters in System Verilog

SystemVerilog
, , ,
1

Hello,

I am using following code.

**module #(parameter FDEPTH=10)(…)
…
out=f1(FIFO);
endmodule

function bit [32:0] f1 (ref bit [31:0] FIFO [FDEPTH])
…
endfunction**

but it is showing me an error that identifier FDEPTH is not declared yet.
That is obvious due to scope, but let me know if there is any way to use
Parameters in function as argument types.

Thanks

2

Yes, you can wrap the function as a static method of a class.

package myutils;
  virtual class #(int DEPTH) u;
    static function bit [32:0] f1 (ref bit [31:0] FIFO [DEPTH])
      ...
    endfunction
  endclass 
endpackage

module #(parameter FDEPTH=10)(...)
  import myutils::*;
  ...
  out=u#(FDEPTH)::f1(FIFO);
endmodule

We strongly recommend putting any declarations outside of a module inside a package.

3

In reply to dave_59:

  If the function f1 is not going to use anywhere except that module, then there is no point in keeping  f1 function in package and importing it.Here we are implicitly declaring the function f1 in that module.

So in this case i would prefer declaring the function f1 in module scope.

4

In reply to cool_cake20:

cool_cake20,

In this case the function is declared outside the module that it is called from. That is the whole point of the original poster’s problem. If it had been declared inside the module, the function would have be parametrized along with the rest of the module. I assume they had a reason for doing it that way because the same function was to be used by other modules.

5

In reply to dave_59:

Thanks Dave :)