Parameters in System Verilog

In reply to cool_cake20:

cool_cake20,

In this case the function is declared outside the module that it is called from. That is the whole point of the original poster’s problem. If it had been declared inside the module, the function would have be parametrized along with the rest of the module. I assume they had a reason for doing it that way because the same function was to be used by other modules.