Parameters in System Verilog

SystemVerilog
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2

Yes, you can wrap the function as a static method of a class.

package myutils;
  virtual class #(int DEPTH) u;
    static function bit [32:0] f1 (ref bit [31:0] FIFO [DEPTH])
      ...
    endfunction
  endclass 
endpackage

module #(parameter FDEPTH=10)(...)
  import myutils::*;
  ...
  out=u#(FDEPTH)::f1(FIFO);
endmodule

We strongly recommend putting any declarations outside of a module inside a package.