Hello everyone ,
my dut is in vhdl , i include it only in test bench ,all other components are in systemverilog , when I compile
it gives me this error
near “;”: syntax error, unexpected ‘;’, expecting STRING_LITERAL or a tick-double-quoted string literal.
is line 1 : which is in vhdl :library ieee ;
in dut I use neither quote nor double quote
thanks
Make sure your VHDL file is actually being compiled as a VHDL file. Simulators typically have different filenames (vlog / vcom) for front end compilation.
In reply to sbellock:
thank you for you reply
vhdl file is comiled before as vhdl and when i include it in testbench it mention the line where is included then error :near “;”: syntax error, unexpected ‘;’, expecting STRING_LITERAL or a tick-double-quoted string literal.
have you ever had such error ?
In reply to Imane EL:
What do you mean by “when i include it in testbench”? How are you doing that? What language is your testbbench. In general, there is no standard for interoperability between different standards, so you need to look at your tools user manual if your testbench is SystemVerilog, but your design is VHDL.
In reply to dave_59:
Hello ,thank you for replying me
well this is how I include it
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "input_if.sv"
`include "output_if.sv"
`include "DUT.vhd"
`include "packet_in.sv"
`include "packet_out.sv"
`include "sequence_in.sv"
`include "sequencer.sv"
`include "driver.sv"
`include "driver_out.sv"
`include "monitor.sv"
`include "monitor_out.sv"
`include "agent.sv"
`include "agent_out.sv"
`include "refmod.sv"
`include "comparator.sv"
`include "env.sv"
`include "simple_test.sv"
//........
DUT is in vhdl but testbench is in systemverilog
In reply to Imane EL:
As Dave stated, you can’t just include a VHDL file in a SystemVerilog package. Your VHDL file needs to be compiled as a separate step in your compilation flow.
In reply to cgales:
actually I have compiled vhdl file using command vcom and systemverilog file using vlog but still give same error
do I have to use signal_spy?so it can solve it or this is a solution of another problem ?
I’ve questa 10.7c
thanks
And you removed
`include "DUT.vhd"
from the package, correct?