In reply to dave_59:
Hello ,thank you for replying me
well this is how I include it
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "input_if.sv"
`include "output_if.sv"
`include "DUT.vhd"
`include "packet_in.sv"
`include "packet_out.sv"
`include "sequence_in.sv"
`include "sequencer.sv"
`include "driver.sv"
`include "driver_out.sv"
`include "monitor.sv"
`include "monitor_out.sv"
`include "agent.sv"
`include "agent_out.sv"
`include "refmod.sv"
`include "comparator.sv"
`include "env.sv"
`include "simple_test.sv"
//........
DUT is in vhdl but testbench is in systemverilog