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  • Multiple clocking events with a time step

Multiple clocking events with a time step

SystemVerilog 6318
Multiple clocking ... 1
MICRO_91
MICRO_91
Full Access
156 posts
January 21, 2023 at 6:39 am

Hi All ,

Section 19.3 of the LRM states :
If the clocking event occurs multiple times in a time step, the coverage point will also be sampled multiple times

I was curious on how a clocking event could occur multiple times in same time step .

Would be helpful if someone could provide a small example of the same

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ben@SystemVerilog.us
ben@SystemVerilog.us
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2600 posts
January 21, 2023 at 3:12 pm

In reply to MICRO_91:
Here is an example where the variable k has 2 events in a time step.

https://www.edaplayground.com/x/gAXc

module m;
  bit [4:0] a;
    bit clk, b=0, c, k, w, q;
    initial forever #5 clk = !clk;
  always @(posedge clk) begin 
     a <= a + 1; b<=!b; c <= 0;  end
 
    ap_1: assert property (@(posedge clk) b |-> c) 
      else begin k=!k; w=!w; end 
// k and w change in the Reactive region 
// ap_2 is scheduled in the Observed region in the loopback 
 
      ap_2: assert property (@(k) b |-> c) 
      else  w=!w;
// ap_2 is processed in the lopback in the Observed region 
// and w toggles again 
//THUS, in that same time step w has 2 transitions 
 
    initial begin
      $dumpfile("dump.vcd"); $dumpvars;
      repeat(6) @(posedge clk);
      $finish;
    end
  endmodule 

If I write the following, I would have clocking event occurs multiple times in a time step,
covergroup g1 @(w);
c: coverpoint color;
endgroup

Ben Cohen
http://www.systemverilog.us/
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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Understanding and Using Immediate Assertions
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SVA Alternative for Complex Assertions
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SVA in a UVM Class-based Environment
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SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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dave_59
dave_59
Forum Moderator
10661 posts
January 21, 2023 at 11:17 pm

In reply to MICRO_91:

There are many convoluted ways.

bit b,c;
initial repeat (20)
               begin
                 c <= !c;
                 @c;
               end
covergroup cg @(poesedge c);
coverpoint b {
  bins bs[2] = {0,1};
}
endgroup
cg cgi=new;

— Dave Rich, Verification Architect, Siemens EDA

MICRO_91
MICRO_91
Full Access
156 posts
January 23, 2023 at 10:19 am

In reply to dave_59:

Hi Dave ,

Your code invoked an interest to understand the Region where sampling occurs :
I tried 2 variations ::

  //  Code 1  ::
  bit [1:0]  a ;   
  bit   clk ;    
 
   covergroup cg1 @( posedge clk ) ; 
      a_auto : coverpoint a ;   
   endgroup
 
   cg1  cg_1  =  new() ;
 
   initial  forever  #5  clk  =  !clk ;
 
   always @ ( posedge clk )  a  <=  a + 1 ;

  //  CODE2  ::
   bit c;   
   initial 
     repeat (2) 
       begin    
         c <= !c; @c;    
       end 
 
   covergroup cg @(posedge c); 
 
      coverpoint c  //  For 0 -> 1 transition , c would be sampled 1
      {   
        bins bs[2] = {0,1};
      }   
 
   endgroup
 
   cg cgi = new ;

For 1st case : 3 bins corresponding to values of a = 0 , 1 , 2 are covered .
For 2nd case : bin corresponding to value of bs[1] is covered .

Can I say the coverpoint expression in sampled in Active region ?

dave_59
dave_59
Forum Moderator
10661 posts
January 23, 2023 at 10:35 am

In reply to MICRO_91:

The sentence before the one you quote in section 19.3 says "a coverage point is sampled the instant the clocking event takes place". This means the covergroup does not care about event regions. The sampling takes place in the region the event occurs.

— Dave Rich, Verification Architect, Siemens EDA

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