In reply to MICRO_91:
Here is an example where the variable k has 2 events in a time step.
module m;
bit [4:0] a;
bit clk, b=0, c, k, w, q;
initial forever #5 clk = !clk;
always @(posedge clk) begin
a <= a + 1; b<=!b; c <= 0; end
ap_1: assert property (@(posedge clk) b |-> c)
else begin k=!k; w=!w; end
// k and w change in the Reactive region
// ap_2 is scheduled in the Observed region in the loopback
ap_2: assert property (@(k) b |-> c)
else w=!w;
// ap_2 is processed in the lopback in the Observed region
// and w toggles again
//THUS, in that same time step w has 2 transitions
initial begin
$dumpfile("dump.vcd"); $dumpvars;
repeat(6) @(posedge clk);
$finish;
end
endmodule
If I write the following, I would have clocking event occurs multiple times in a time step,
Your code invoked an interest to understand the Region where sampling occurs :
I tried 2 variations ::
// Code 1 ::
bit [1:0] a ;
bit clk ;
covergroup cg1 @( posedge clk ) ;
a_auto : coverpoint a ;
endgroup
cg1 cg_1 = new() ;
initial forever #5 clk = !clk ;
always @ ( posedge clk ) a <= a + 1 ;
// CODE2 ::
bit c;
initial
repeat (2)
begin
c <= !c; @c;
end
covergroup cg @(posedge c);
coverpoint c // For 0 -> 1 transition , c would be sampled 1
{
bins bs[2] = {0,1};
}
endgroup
cg cgi = new ;
For 1st case : 3 bins corresponding to values of a = 0 , 1 , 2 are covered .
For 2nd case : bin corresponding to value of bs[1] is covered .
Can I say the coverpoint expression in sampled in Active region ?
The sentence before the one you quote in section 19.3 says “a coverage point is sampled the instant the clocking event takes place”. This means the covergroup does not care about event regions. The sampling takes place in the region the event occurs.