Hi,
In practice, what is the common way to check functionality of a clock divider(e.g. freq: clk_o=1/2 or 1/4 clk_i) using SVA. given clk_i, clk_o and ratio, could anybody provide an example?
Thanks in advance.
In reply to philerpeng:
You need to start with the requirements. Thus, for a 1/2 clock, you could first write something like: chall toggle
- Given a system master clock “clk”, there shall be a half clock “clk2” and a quarter clock “clk4”, all of which are generated from the master clock.
- “clk2” clock shall toggle at each posedge of the master clock “clk”, and its output shall have a maximum hold time of Xns.
- “Clk4” shall toggle when “clk2==0” at the posedge of the master clock “clk”. “clk4” output shall have a maximum hold time of Xns.
Once you have a spec, it becomes trivial to write assertions. Remember, the assertions are a reflection of the requirements.
//
ap_clk2: assert property(@(posedge clk) ##1 |-> clk2==!$past(clk2));
ap_clk4: assert property(@(posedge clk) #2 clk2==0 |->
clk4==!$past(clk4,2));
// The antecedent ##1 and ##2 are just used for initialization, since the clk2 and clk4 have not started.
// You need to look at the initial conditions.
// This code is not tested, but it looks ok to me. Needs testing anyway.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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In reply to ben@SystemVerilog.us:
Hi Ben,
I just learn by other’s examples.
So for the first assertion, it will work but the question comes if the clk2 toggles before the next edge of clk1, the assertion will still pass.
How can one make sure the clk2 is actually 1/2 of clk1 but not an approx?
In reply to devil47:
You can write logic that measures the duration of the clocks
Edges and the relationships (delays) between clock edges of clocks.
They should be within acceptable limits.
See. checking clock period using system verilog assertion | Verification Academy
Ben systemverilog.us