How to verify clock divider using SVA

SystemVerilog
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4

In reply to ben@SystemVerilog.us:

Hi Ben,

I just learn by other’s examples.
So for the first assertion, it will work but the question comes if the clk2 toggles before the next edge of clk1, the assertion will still pass.
How can one make sure the clk2 is actually 1/2 of clk1 but not an approx?