How to model a bus behavior with enable signal in testbench

SystemVerilog
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1

If a bus with data and enable asychronous to clock, is it correct to write as follows to catch data from DUT ?

@(posedge clock)
if(enable)
bfm_data = data ;

If enable is rising or falling, what’s the result of if(enable)?

Another question is when a statement is executed if the statement in two clock event ?
For example:

@(posedge clock)
A
@(posedge clock)

Is statement A executed at just right after 1st rising clock or 2nd rising clock ?

2

See the following pages extracted from my SVA book on the timing regions, and when things get executed; the image is self-explanatory.

If that is not clear, re-ask your question.
You may also want to consider a clocking block, below is an example.


parameter SIZE=8; 
interface test_if (input logic clk);
    logic ld; 
    logic[SIZE-1:0] d_in; 
    logic[SIZE-1:0] r_out, r_out2;
    wire logic[SIZE-1:0] data1, data2, data3; 
    clocking driver_cb @ (posedge clk);
        default input #2 output #3; // setup, hold
        output data1,r_out2; 
        input d_in;
        inout data2;
    endclocking : driver_cb
    modport drvr_if_mp (clocking driver_cb);
endinterface :test_if

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to ben@SystemVerilog.us:

Hi Ben,

In gate level simulations, such as worst and best, is it advisable to turn-off the skews? I mean the “default input #2 output #3”?
This is because in gate level simulation gate delays and wire delays are already included.

Regards,
Reuben

4

In reply to Reuben:

In gate level simulations, such as worst and best, is it advisable to turn-off the skews? I mean the “default input #2 output #3”?
This is because in gate level simulation gate delays and wire delays are already included.

Two answers to this question:

  1. Yes to “is it advisable to turn-off the skews?”
    Note though, that FPGAs and ASICs have clock trees that buffer the input clock and distribute it throughout the sea of gates so as to minimize the skews between clocks at the registers. Thus, if in your gate level simulation with SVA you use the input clock, the gate level clocking will have some additional delays, which is equivalent to additional negative input skews since the inputs will be sampled by SVA a couple or so gate-level clocks before the actual FF clocks. That should be OK.
  2. Typically though, static timing analyzers are used to verify timing within the design, as that will define the maximum frequency at which the design will work. Also, equivalency checking tools are used to verify that the gate level model is equivalent to the RTl. An example of tools is at http://www.realintent.com/real-intent-products/

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115