See the following pages extracted from my SVA book on the timing regions, and when things get executed; the image is self-explanatory.
If that is not clear, re-ask your question.
You may also want to consider a clocking block, below is an example.
parameter SIZE=8;
interface test_if (input logic clk);
logic ld;
logic[SIZE-1:0] d_in;
logic[SIZE-1:0] r_out, r_out2;
wire logic[SIZE-1:0] data1, data2, data3;
clocking driver_cb @ (posedge clk);
default input #2 output #3; // setup, hold
output data1,r_out2;
input d_in;
inout data2;
endclocking : driver_cb
modport drvr_if_mp (clocking driver_cb);
endinterface :test_if
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115