How to model a bus behavior with enable signal in testbench

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben,

In gate level simulations, such as worst and best, is it advisable to turn-off the skews? I mean the “default input #2 output #3”?
This is because in gate level simulation gate delays and wire delays are already included.

Regards,
Reuben