How to instantiate the same assertion for multiple registers

SystemVerilog
,
1

Hi
I am trying to assert the same generic assertion for multiple registers
So I have io_conf1_reg, io_conf2_reg registers and for each of these registers -I want to assert the same assertion 2 times:

Assertion: AST_REG_WRITE_CHECK : assert property (REG_WRITE_CHECK_DUE_TO_TRIGGER(clk, register_disable_conditions , register_to_write , register_write_condition));

For the two registers -I want the following outcome:

AST_REG_WRITE_CHECK : assert property (REG_WRITE_CHECK_DUE_TO_TRIGGER(clk, register_disable_conditions , io_conf1_reg , register_write_condition));
AST_REG_WRITE_CHECK : assert property (REG_WRITE_CHECK_DUE_TO_TRIGGER(clk, register_disable_conditions , io_conf2_reg , register_write_condition));

Can someone recommend a way of doing this- note I have only two registers here-in reality I need to repeat this assertion about 30 times for 30 different registers
I have tried using define macro in a generate loop- however that does not use the actual generate loop value

2

In reply to sa_1:

Unfortunately there is no easy way to do this unless you can covert the register instance names into an array.

3

In reply to dave_59:

Thanks Dave
Will appreciate if you could give me an example and show it being used in a genvar loop
Thanks in advance

4

In reply to sa_1:

logic [31:0] io_config_reg[NUMBER_OF_CONFIG_REGS];

for(genvar index=0; index < NUMBER_OF_CONFIG_REGS; index++) begin : AST_REG_WRITE_CHECK
  assert property (REG_WRITE_CHECK_DUE_TO_TRIGGER(clk, register_disable_conditions , io_conf_reg[index] , register_write_condition));
end