How to access hierarchical signals in VHDL design from SystemVerilog TestBench?

SystemVerilog
1

Hi All,

My design in VHDL. My TestBench in SystemVerilog.

Actually, I have a problem to access the internal (hierarchical) signals in VHDL design from my TestBench.

Here is the code:

initial begin
$display("flr_cnt0: %0h", tb_bit_mgr_wrp.i_bit_mgr_wrp.i_bit_mgr.i_filter.gen_flt(0).gen_flr_cnt.i_flr_cnt.flr_cnt);
end

Here is an error, which I receive during the simulation:

** Error: (vsim-3919) D:/units/bit/tb/mon//mon_flr_cnt.v(20): Not permitted to resolve Verilog reference to VHDL item gen_flt in tb_bit_mgr_wrp.i_bit_mgr_wrp.i_bit_mgr.i_filter.gen_flt.
#    Time: 0 ps  Iteration: 0  Instance: /tb_bit_mgr_wrp File: D:/units/bit/tb/tb_bit_mgr_wrp.v

How to solve? How to access hierarchical signals in VHDL design from SystemVerilog TestBench?

Thank you!

2

In reply to dmitryl:

It’s sad, but there is no standard interface for mixing references between different language standards. Consult the user manual of the tool for what it allows.

3

In reply to dave_59:
Hi dave

can’t we use DPI(direct programming interface)?

4

In reply to ASICverif:

I think you meant ask about VPI as DPI has no access outside to the design other than through passing arguments to C routines.

And the answer to that is the same.

5

If you’re using Questa (which the log file says), there’s the $init_signal_spy function you can read about.

6

In reply to Tudor Timi:

$init_signal_spy, sure, thanks!