Filtering zero ns glitch

SystemVerilog
1

HI,
Is there a way that i can filter 0ns glitch (0->1->0 or 1->0->1) on a signal.

assign #0 sig_glitchless = sig; //Didn't worked.

Thanking in Advance

2

In reply to ysaini:

Hi,

One hack is to wait for values to settle down within same time slot. In your case, only 2 transitions are shown so you need #0 delay twice!

You estimate depth of your logic and say number of zero delay events it might trigger, and take number of #0 more than this value. This is not a robust way to do things, but it works.

always@(*)
begin
  repeat(num) #0;
  sig_glitchless = sig;
end

To make sure your resultant signal is filtered of #0s, create a monitor/assertion logic to detect zero delay gitch. Keep increasing repeat num of #0, until this assertion passes everytime.

3

In reply to MayurKubavat:
Using #0 in repeat loop is one of the worst things you can do. It’s bad for performance, and it usually creates more problems downstream that you will wind up adding more #0’s.

If this is truly an asynchronous signal, you can add a real delay to it.

assign #1ps sig_glitchless = sig;

Any glitch less than 1 ps will get filtered out.

Another thing you could do is add a delta step using a non-blocking event

always @sig
    begin
      event e;
    ->>e;
    @e sig_glitchless = sig;
    end
4

In reply to dave_59:

assign #1ps sig_glitchless = sig;


Above code filters any glitches less than 1ps, and also delays the original signal by 1ps. So I think this is not what one should look for.

Also, non-blocking delta step might not work in conditions where Zero delay events are loop back from preceded non-blocking statement. For e.g.

//These statements creates a loopback from non-blocking 
//event region to active event region
   sig <= 0;
#0 sig <= 1;
#0 sig  = 0;
#0 sig  = 1;

So I guess here, adding multiple #0s(Inactive Events) also might not work!

5

Thanks Dave and Mayur for the suggestions.

I tried following code and it was able to filter 0 ns glitch.

always @(*) sig_glitchless <= #0 sig;

Cannot use below code:

assign #1ps sig_glitchless = sig;
  1. Due to dependency on timescale
  2. Signal get delay by 1ps which i do not want
6

In reply to ysaini:
FYI, #0 is ignored in a non-blocking assignment so you can write as

always @(*) sig_glitchless <= sig;
7

In reply to dave_59:

Dave, Thanks for sharing this info. I tried your solution and it worked.

Thanks Again!

8

In reply to dave_59:

In reply to ysaini:
FYI, #0 is ignored in a non-blocking assignment so you can write as

always @(*) sig_glitchless <= sig;

This didn’t work for me, both with and without the #0. Using Questa 10.7e.