Filtering zero ns glitch

SystemVerilog
5

Thanks Dave and Mayur for the suggestions.

I tried following code and it was able to filter 0 ns glitch.

always @(*) sig_glitchless <= #0 sig;

Cannot use below code:

assign #1ps sig_glitchless = sig;
  1. Due to dependency on timescale
  2. Signal get delay by 1ps which i do not want