Filtering zero ns glitch

SystemVerilog
2

In reply to ysaini:

Hi,

One hack is to wait for values to settle down within same time slot. In your case, only 2 transitions are shown so you need #0 delay twice!

You estimate depth of your logic and say number of zero delay events it might trigger, and take number of #0 more than this value. This is not a robust way to do things, but it works.

always@(*)
begin
  repeat(num) #0;
  sig_glitchless = sig;
end

To make sure your resultant signal is filtered of #0s, create a monitor/assertion logic to detect zero delay gitch. Keep increasing repeat num of #0, until this assertion passes everytime.