Filtering zero ns glitch

SystemVerilog
3

In reply to MayurKubavat:
Using #0 in repeat loop is one of the worst things you can do. It’s bad for performance, and it usually creates more problems downstream that you will wind up adding more #0’s.

If this is truly an asynchronous signal, you can add a real delay to it.

assign #1ps sig_glitchless = sig;

Any glitch less than 1 ps will get filtered out.

Another thing you could do is add a delta step using a non-blocking event

always @sig
    begin
      event e;
    ->>e;
    @e sig_glitchless = sig;
    end