Executing events at start of sim time

SystemVerilog
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Hi ,

In system verilog, we have #0 to tell the compiler to execute a particular code at the end of simulation time(after executing all other events)
Is there any construct to tell the simulator to execute certain things at the start of simulation time.
(before executing any other events)

regards,
bibin

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In reply to Bibin Paul:
Hi Bibin,
The #0 delay is not executing at the end of simulation but in the “inactive” region.
And could you please specify more about your purpose.

The cummings paper “SystemVerilog Event Regions, Race Avoidance & Guidelines” will help you to understand the SV event regions.

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In reply to bdreku:

In reply to Bibin Paul:
Hi Bibin,
The #0 delay is not executing at the end of simulation but in the “inactive” region.
And could you please specify more about your purpose.
The cummings paper “SystemVerilog Event Regions, Race Avoidance & Guidelines” will help you to understand the SV event regions.

Hi Modh,

Thanks for the reply, i have a number of events from parallel threads to be executed on the same edge of the clock. I am sure a set of stuffs need to execute ahead of others(I have clarity on which needs to be executed before the other). Right now, they are in parallel threads(which are in forever-fork-join_none/analysis port functions in my scoreboard). So i don’t want to make it sequential either.

Thanks.

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In reply to Bibin Paul:
You can use systemverilog events, semaphore or flag to provide a synchronization between parallel threads.