In reply to bdreku:
In reply to Bibin Paul:
Hi Bibin,
The #0 delay is not executing at the end of simulation but in the “inactive” region.
And could you please specify more about your purpose.
The cummings paper “SystemVerilog Event Regions, Race Avoidance & Guidelines” will help you to understand the SV event regions.
Hi Modh,
Thanks for the reply, i have a number of events from parallel threads to be executed on the same edge of the clock. I am sure a set of stuffs need to execute ahead of others(I have clarity on which needs to be executed before the other). Right now, they are in parallel threads(which are in forever-fork-join_none/analysis port functions in my scoreboard). So i don’t want to make it sequential either.
Thanks.