Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • Continuous Integration - March 28th
      • Questa Verification IQ - April 11th
      • SystemVerilog Assertions
      • SoC Design & Functional Safety Flow
      • 2022 Functional Verification Study
      • Design Solutions as a Sleep Aid
      • CDC and RDC Assist
      • Formal and the Next Normal
      • Protocol and Memory Interface Verification
      • Webinar Calendar

    • On-Demand Library

      • Practical Flows for Continuous Integration
      • Lint vs Formal AutoCheck
      • The Three Pillars of Intent-Focused Insight
      • Formal Verification Made Easy
      • Fix FPGA Failures Faster
      • HPC Protocols & Memories
      • FPGA Design Challenges
      • High Defect Coverage
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Complex Safety Architectures
      • Data Independence and Non-Determinism
      • Hierarchical CDC+RDC
      • All On-Demand Recordings

    • Recording Archive

      • Aerospace & Defense Tech Day
      • Exhaustive Scoreboarding
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • Visualizer Debug Environment
      • Preparing for PCIe 6.0: Parts I & II
      • Automotive Functional Safety Forum
      • Siemens EDA Functional Verification
      • Improving Your SystemVerilog & UVM Skills
      • All Webinar Topics

    • Conferences & WRG

      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences

    • Siemens EDA Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us

    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
Ask a Question
SystemVerilog
  • Home
  • Forums
  • SystemVerilog
  • cover group

cover group

SystemVerilog 6308
#SystemVerilog ... 19
rakesh reddy
rakesh reddy
Full Access
30 posts
December 11, 2016 at 5:43 am 

module def_cov_point;
 
class trx;
rand bit [2:0]a;
rand bit [3:0]b;
 
 
endclass
 
 
covergroup c;
  ADDRESS : coverpoint tr.a+tr.b{
    // This should create 11 bins
    bins low[]          = {[0:10]};
    // This should create 10 bins
    bins med[]         = {[11:20]};
  }
 
endgroup
trx tr;
c c1;
 
initial begin 
tr = new;
c1 = new;
repeat(10) begin 
tr.randomize();
c1.sample();
 
end
 
end
endmodule

here in this code, onlky 15 bins are getting created why not 20 bins as specified in code?

Replies

Log In to Reply
KranthiDV
KranthiDV
Full Access
51 posts
December 11, 2016 at 7:10 am

In reply to rakesh reddy:

tr.a+tr.b will be converted to 4 bit output. so 16 bins max.

rakesh reddy
rakesh reddy
Full Access
30 posts
December 11, 2016 at 9:49 am

In reply to kranthi445:

But these 2 lines
bins low[] = {[0:10]};
// This should create 10 bins
bins med[] = {[11:20]};
are used to create 20 bins not 16 bins

dave_59
dave_59
Forum Moderator
10658 posts
December 11, 2016 at 6:31 pm

In reply to rakesh reddy:Because the bin values 17, 18, 19, and 20 are eliminated because they are out-of-bounds for the range specified.

— Dave Rich, Verification Architect, Siemens EDA

KranthiDV
KranthiDV
Full Access
51 posts
December 11, 2016 at 7:10 pm

In reply to rakesh reddy:

bins med[]= [{11:20}]; will create bins from [{11:15}] bins 16,17,18,19,20 are eliminated because your 4bit output can not hold values of 16,17,18,19,20.

bins low[]={[0:11]} // this will create 11 bins 0 to 10
bins med[]=[{11:20}] // this will create 5 bins 11 to 15

rakesh reddy
rakesh reddy
Full Access
30 posts
December 12, 2016 at 12:28 am

Hi Dave,

i am adding a 3 bit number and a 4 bit number, so effective number of bins will be 16.but adding a 4 bit and 3 bit number may result in 5 bit number (Eg: 15+8 = 23 which is maximum possible result)
So i need to create 23 bins
So bins len[] = {[0:22]}
can be used to create 23 bins
Is this Correct?

dave_59
dave_59
Forum Moderator
10658 posts
December 12, 2016 at 12:39 am

In reply to rakesh reddy:Except that according to the 1800-2012 LRM table 11-21, the length of a + b is max(L(a),L(b)) in a self-determined context. You need to write

  ADDRESS : coverpoint 5'(tr.a+tr.b) {
    // This should create 11 bins
    bins low[]          = {[0:10]};
    // This should create 10 bins
    bins med[]         = {[11:20]};
  }

— Dave Rich, Verification Architect, Siemens EDA

rakesh reddy
rakesh reddy
Full Access
30 posts
December 12, 2016 at 1:39 am

In reply to dave_59:
if i do this then 32 bins are created i need only 23 bins

KranthiDV
KranthiDV
Full Access
51 posts
December 12, 2016 at 2:02 am

In reply to rakesh reddy:

use
options.auto_bin_max=24

rakesh reddy
rakesh reddy
Full Access
30 posts
December 12, 2016 at 2:29 am

In reply to kranthi445:

See the following example from LRM

bit [9:0] v_a; 
covergroup 
cg @(
posedge 
clk);
coverpoint
 v_a
{
bins 
a = { [0:63],65 };
bins b[] = { [127:150],[148:191] };    // note overlapping values
bins c[] = { 200,201,202 };
bins d = { [1000:$] }; 
bins others[] = 
default;
}
endgroup

In the example above, the first
bins
construct associates bin awith the values of variable v_abetween 0 and63, and the value 65. The second binsconstruct creates a set of 65 bins b[127], b[128],...b[191]. Like-wise, the third bins construct creates 3 bins: c[200], c[201], and c[202].
The fourth bins construct asso-ciates bin d with the values between 1000 and 1023 ($ represents the maximum value of v_a).
Every value thatdoes not match bins a, b[], c[], or d[]
is added into its own distinct bin

In this way i also want to create 23 bins but it is not happening

dave_59
dave_59
Forum Moderator
10658 posts
December 12, 2016 at 7:43 am

In reply to rakesh reddy:
Can you show the code again? I get 21 bins (values 0-20)

— Dave Rich, Verification Architect, Siemens EDA

rakesh reddy
rakesh reddy
Full Access
30 posts
December 12, 2016 at 8:21 am

In reply to dave_59:

module def_cov_point;
 
class trx;
rand bit [2:0]a;
rand bit [3:0]b;
 
 
endclass
 
 
covergroup c;
  ADDRESS : coverpoint tr.a+tr.b{
    // This should create 11 bins
    bins low[]          = {[0:10]};
    // This should create 10 bins
    bins med[]         = {[11:20]};
  }
 
endgroup
trx tr;
c c1;
 
initial begin 
tr = new;
c1 = new;
repeat(10) begin 
tr.randomize();
c1.sample();
 
end
 
end
endmodule
dave_59
dave_59
Forum Moderator
10658 posts
December 12, 2016 at 8:25 am

In reply to rakesh reddy:

But you didn't add the cast as I said my post.

— Dave Rich, Verification Architect, Siemens EDA

Siemens Digital Industries Software

Siemens Digital Industries Software

#TodayMeetsTomorrow

Portfolio

  • Cloud
  • Mendix
  • Electronic Design Automation
  • MindSphere
  • Design, Manufacturing and PLM Software
  • View all Portfolio

Explore

  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Customer Stories
  • Partners
  • Trust Center

Contact

  • VA - Contact Us
  • PLM - Contact Us
  • EDA - Contact Us
  • Worldwide Offices
  • Support Center
  • Give us Feedback
© Siemens 2023
Terms of Use Privacy Statement Cookie Statement DMCA